Peripheral devices of a host are generally used by connecting with the host. Each of the peripheral devices includes a communication interface which transmits and receives data to and from the host. The communication interface includes a data synchronizer which synchronizes data synchronized with a first clock signal with a second clock differing from the first clock.
If peripheral devices are used by connecting with a plurality of hosts, a multiport interface must be used as a communication interface for the peripheral devices. Suppose the multiport interface includes a first port and a second port and is connected to a first host and a second host via the first port and second port, respectively. Such a multiport interface includes a first data synchronizer applied to a first link layer (described later) of the first port and a second data synchronizer applied to a second link layer (described later) of the second port.
The first port is composed of a first link layer and a first transport layer. The second port is composed of a second link layer and a second transport layer. The multiport interface has only one application layer. The reason is that one application layer is caused to collectively manage commands received by the individual ports (first and second ports). Therefore, a clock signal input to the application layer is preferably for one route; otherwise a synchronizer corresponding to each of the first and second synchronizers is needed in the application layer.
Suppose a first clock signal CLK_A0 and a second clock signal CLK_B0 are input to the first link layer and a first clock signal CLK_A1 and a second clock signal CLK_B1 are input to the second link layer. Here, the frequency of the first clock signal CLK_A0 is not necessarily the same as that of the first clock signal CLK_A1. Similarly, the frequency of the second clock signal CLK_B0 is not necessarily the same as that of the second clock signal CLK_B1.
Therefore, a third clock signal CLK_C differing in frequency from both of the second clock signals CLK_B0 and CLK_B1 is input to an application layer common to the first and second ports. In this case, the application layer requires a synchronizer for synchronizing second clock signal CLK_B0 and third clock signal CLK_C and a synchronizer for synchronizing second clock signal CLK_B1 and third clock signal CLK_C.
If the allowable frequency range of the second clock signals CLK_B0 and CLK_B1 can be extended, a second clock signal CLK_B can be used in both the first and second link layers (first and second data synchronizers) in place of the second clock signals CLK_B0 and CLK_B1. In this case, the second clock signal CLK_B can be used in an application layer common to the first and second ports and a third clock signal CLK_C requiring an additional synchronizer need not be used. Accordingly, it is hoped that the allowable frequency range of the second clock signal will be extended in the data synchronizer.